Ch. Suresh, Pesala Venkata Sai Ganesh, Suram Naga Mukesh Reddy, Pambakula Manohar 02 04 Orthogonal Time Frequency Space OTFS modulation is a promising technique known for its robustness in timevarying channels making it wellsuited for highmobility communication environments This project focuses on the design and hardware implementation of a lowcomplexity Zero Forcing ZF equalizer for a SingleInput SingleOutput SISO OTFS system To reduce computational complexity and hardware overhead we propose a Very Large Scale Integration VLSI architecture that incorporates parallel processing and resource optimization techniques A key feature of the design is the use of a backtoback Fast Fourier Transform FFT and Inverse FFT IFFT structure which simplifies matrix inversion operations and allows for efficient updates without significantly degrading performance The architecture is carefully crafted to support realtime processing while satisfying area and latency requirements Through extensive simulations and evaluations we study the tradeoffs between reduced complexity and equalization performance Performance metrics such as Bit Error Rate BER latency and hardware area are used to evaluate the design Synthesis results on a Xilinx 7vx485tffg11571 FPGA demonstrate the effectiveness of the proposed architecture achieving a latency of 440 ns at a 100 MHz clock frequency utilizing 249843 LookUp Tables LUTs and 74611 FlipFlops FFs Copyright (c) Journal of Science Engineering Technology and Management Science. All rights reserved 2026