Gundala Praveena, Koppula Manasa 03 07 The increasing adoption of highdimensional data processing in image analysis wireless communication machine learning biomedical signal processing and realtime embedded systems has significantly increased the demand for efficient Singular Value Decomposition SVD hardware accelerators SVD plays a critical role in applications such as feature extraction noise reduction image compression adaptive filtering MIMO communication systems pattern recognition and data analytics where rapid and accurate matrix decomposition is essential for realtime decisionmaking However existing SVD architectures predominantly rely on sequential largestelement search mechanisms conventional COordinate Rotation DIgital Computer CORDIC based rotation processors and limited memory organizations resulting in increased search latency memory access bottlenecks higher computational complexity reduced throughput and slower convergence for largescale matrices To address these limitations this work proposes a novel parallel SVD architecture incorporating an Iterative Vector Rotation Unit IVRU Parallel Scan Search Module PSSM Address and Data Synchronization Unit ADSU and MultiBank Memory MBM The PSSM accelerates dominant element identification through concurrent comparisons while the MBM enables simultaneous read and write operations to eliminate memory contention The ADSU ensures synchronized and conflictfree communication among processing modules and the IVRU performs efficient iterative vector rotations for rapid matrix diagonalization The integration of these modules significantly reduces computational latency improves memory bandwidth utilization enhances convergence speed increases processing throughput and provides a scalable hardware platform for highperformance realtime SVD computation in advanced signal processing and intelligent computing applications Copyright (c) Journal of Science Engineering Technology and Management Science. All rights reserved 2026